system verilog - Do delta cycles occur at intermediate stages in SystemVerilog? - Stack Overflow

In Stuart Sutherland's RTL Modelling with SystemVerilog for Simulation and Synthesis, the process for evaluating events in the different event regions within a given simulation time slot is explained. In particular, it's explained that

As events are processed in a later [event] region, they can possibly schedule new events in a previous region. After the later region has been processed, simulation will cycle back through the event regions to process any newly scheduled events. The itera­ tions through all event regions will continue until all regions are empty (i.e. no new events for that moment of simulation time are being scheduled).

My question is about when exactly this cycling happens. Suppose for example we are in the NBA region and e.g. a flip-flop's Q output is updated, and that in turn drives some gate so that an active region event is scheduled in that same simulation time slot. This NBA region then ends some time later. Does the SV standard dictate that the simulator go back to the active region immediately, or does it attend to event regions after the NBA region before cycling back? I imagine the answer is the former (so that $monitor statements indeed end a given simulation time slot) but I'm not quite sure how to test it.

In Stuart Sutherland's RTL Modelling with SystemVerilog for Simulation and Synthesis, the process for evaluating events in the different event regions within a given simulation time slot is explained. In particular, it's explained that

As events are processed in a later [event] region, they can possibly schedule new events in a previous region. After the later region has been processed, simulation will cycle back through the event regions to process any newly scheduled events. The itera­ tions through all event regions will continue until all regions are empty (i.e. no new events for that moment of simulation time are being scheduled).

My question is about when exactly this cycling happens. Suppose for example we are in the NBA region and e.g. a flip-flop's Q output is updated, and that in turn drives some gate so that an active region event is scheduled in that same simulation time slot. This NBA region then ends some time later. Does the SV standard dictate that the simulator go back to the active region immediately, or does it attend to event regions after the NBA region before cycling back? I imagine the answer is the former (so that $monitor statements indeed end a given simulation time slot) but I'm not quite sure how to test it.

• system-verilog

Share Improve this question Follow asked yesterday EE18EE18 20311 silver badge77 bronze badges

Add a comment  | 

1 Answer 1

Sorted by: Reset to default 1

Figure 4-1—Event scheduling regions and section 4.5 SystemVerilog simulation reference algorithm specify how the simulator moves between the different event regions.

The LRM says that an event region must be emptied before moving to another region. With a couple of exceptions, the algorithm will go to the earliest non-empty region.